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W941232AD 1M x 4 BANKS x 32 BIT DDR SDRAM
1. GENERAL DESCRIPTION
W941232AD is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 1,048,576 words x 4 banks x 32 bits. Using pipelined architecture and 0.175 m process technology, W941232AD delivers a data bandwidth of up to 800M words per second (-5). For different application, W941232AD was sorted into the following speed grades: -5. The -5 parts can run up to 200 MHz/CL3. All inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. And Write and Read data are synschronized with the both edges of DQS (Data Strobe). By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W941232AD is ideal for main memory in high performance applications.
2. FEATURES
* 2.5V - 2.95V Power Supply * Double Data Rate architecture; two data transfers per clock cycle * * * * * * * * * * *
Differential clock inputs (CLK and CLK ) DQS is edge-aligned with data for Read; center-aligned with data for Write CAS Latency: 3 and 4 Burst Length: 2, 4 and 8 Auto Refresh and Self Refresh Precharged Power Down and Active Power Down Write Data Mask Write Latency = 1 4K Refresh cycles / 64 mS Interface: SSTL-2 Packaged in LQFP 100-pin, 630 x 866 mil, 0.65 mm pin pitch
3. KEY PARAMETERS
SYMBOL DESCRIPTION MIN./ MAX. -5
tCK tRAS tRC IDD1 IDD4 IDD6
Clock Cycle Time
CL = 3 CL = 4
min. min. min. min. max. max. max.
5 nS 40 nS 65 nS 330 490 1.5
Active to Precharge Command Period Active to Ref/Active Command Period Operation Current (Single bank) Burst Operation Current Self-Refresh Current
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Publication Release Date: January 24, 2003 Revision A1
W941232AD
4. PIN CONFIGURATION
VDDQ
VDDQ
DQ31
DQ30
DQ29
VSSQ
VSSQ
VSSQ
DQS
DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DM0 DM2 WE CAS RAS CS BA0 BA1
1 2 3 4 5 6 7 8 9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
DQ2 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 A0
30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQ1 A2
DQ0
VDD
VSS
N.C
N.C
N.C
N.C
N.C
N.C
DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ VREF DM3 DM1 CLK CLK CKE N.C A8/AP
A1
A3
VDD
A10
A11
N.C
N.C
N.C
-2-
N.C
N.C
N.C
N.C
A9
VSS
A4
A5
A6
A7
W941232AD
5. PIN DESCRIPTION
PIN NUMBER 31-34, 36, 37, 45, 47 - 51 29, 30 97, 98, 100, 1, 3, 4, 6, 7, 9, 10, 12, 13, 17, 18, 20, 21, 60, 61, 63, 64, 68, 69, 71, 72, 74, 75, 77, 78, 80, 81, 83, 84 94 PIN NAME A0 - A11 FUNCTION Address DESCRIPTION Multiplexed pins for row and column address. Row address: A0 - A11. Column address: A0 - A7. (A8 is used for Auto Precharge) Select bank to activate during row address latch time, or bank BA0, BA1 Bank Address to read/write during column address latch time.
DQ0 - DQ31
Data Input/ Output
The DQ0 - DQ31 input and output data are synchronized with both edges of DQS.
DQS
Data Strobe
DQS is Bi-directional signal. DQS is input signal during write operation and output signal during read operation. It is Edgealigned with read data, Center-aligned with write data. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command inputs (along with CS ) define the command being entered. DM is an input mask signal for writes data. When DM is asserted "high" in burst write, the input data is masked. DM is synchronized with both edges of DQS. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of CLK .
28
CS RAS , CAS , WE
Chip Select Command Inputs Write Mask Differential Clock Inputs
25, 26, 27
23, 24, 56, 57
DM0 - DM3 CLK, CLK
54, 55
53
CKE
CKE controls the clock activation and deactivation. CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry CKE must be maintained high throughout Clock Enable READ and WRITE accesses. Input buffers, excluding CLK, CLK and CKE are disabled during POWER-DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. Reference Voltage VREF is reference voltage for inputs.
58 15, 35, 65, 96 16, 46, 66, 85 2, 8, 14, 22, 59, 67, 73, 79, 86, 95 5, 11, 19, 62, 70, 76, 82, 92, 99 38-44, 87-91, 93
VREF VDD VSS VDDQ VSSQ NC
Power Power for logic circuit inside DDR SDRAM. (+2.5 - 2.95V) Ground Ground for logic circuit inside DDR SDRAM. Power (+2.5 - Separated power from VDD, used for output buffer, to improve 2.95V) for I/O noise immunity.. Buffer Ground for I/O Buffer No Connection Separated ground from VSS, used for output buffer, to improve noise immunity.. No connection
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Publication Release Date: January 24, 2003 Revision A1
W941232AD
6. BLOCK DIAGRAM
CLK CLK
DLL CLOCK BUFFER
CKE
CS RAS CAS WE
COMMAND
CONTROL SIGNAL GENERATOR
DECODER COLUMN DECODER R O W D E C O D MODE REGISTER ADDRESS BUFFER R O W D E C O D COLUMN DECODER
A8
CELL ARRAY BANK #0
CELL ARRAY BANK #1
A0 A7, A9,A10, A11 BA0 BA1
SENSE AMPLIFIER
SENSE AMPLIFIER
Prefetch Register DATA CONTROL CIRCUIT REFRESH COUNTER COLUMN COUNTER
DQ BUFFER
DQ0 DQn DQS DMn
COLUMN DECODER R O W D E C O D R O W D E C O D
COLUMN DECODER
CELL ARRAY BANK #2
CELL ARRAY BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: The cell array configuration is 4096 * 256 * 32
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W941232AD
7. DC CHARACTERISTICS
Absolute Maximum Ratings
SYMBOL VIN VOUT VDD VDDQ TOPR TSTG TSOLDER PD IOUT PARAMETER Input Voltage Relative to Vss Output Voltage Relative to Vss Power Supply Voltage Relative to Vss I/O Power Supply Voltage relative to Vss Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current RATING -0.3 - VDD +0.3 -0.3 - VDDQ +0.3 -0.3 - 3.6 -0.3 - 3.6 0 - 70 -55 - 150 260 1 50 UNIT V V V V C C C W mA NOTES 1 1
1 1 1 1 1 1 1
Recommended DC Operating Conditons
(VDD/VDDQ =2.5 - 2.95VV 5%, TA = 0 to 70C)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTES
VDD VDDQ VREF VTT VIH (DC) VIL (DC) VICK (DC) VID (DC) VIH (AC) VIL (AC) VID (AC) VX (AC) VISO (AC)
Supply Voltage Supply Voltage Input Reference Voltage Termination Voltage (System) Input High Voltage (DC) Input Low Voltage (DC) Differential Clock DC Input Voltage Input Differential Voltage CLK and CLK inputs (DC) Input High Voltage (AC) Input Low Voltage (AC) Input Differential Voltage CLK and CLK inputs (AC) Differential AC input Cross Point Voltage Differential Clock AC Middle Point
2.5 2.5 0.49 x VDDQ VREF -0.04 VREF +0.15 -0.3 -0.3 0.36 VREF +0.31 0.7 VDDQ/2 -0.2 VDDQ/2 -0.2
0.50 x VDDQ VREF -
2.95 2.95 0.51 x VDDQ VREF +0.04 VDDQ +0.3 VREF - 0.15 VDDQ +0.3 VDDQ +0.6 VREF - 0.31 VDDQ +0.6 VDDQ/2 +0.2 VDDQ/2 +0.2
V V V V V V V V V V V V V
2 2 2, 3 2, 8 2 2 15 13, 15 2 2 13, 15 12, 15 14, 15
Note: Undershoot Limit: VIL(min) = -0.9V with a pulse width < 5 nS Overshoot Limit: VIH(max) = VDDQ +0.9V with a pulse width < 5 nS VIH(DC) and VIL(DC) are levels to maintain the current logic state. VIH(AC) and VIL(AC) are levels to change to the new logic state.
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Publication Release Date: January 24, 2003 Revision A1
W941232AD
Capacitance
(VDD/VDDQ = 2.5 - 2.95V, f = 1 MHz, TA = 25C)
SYMBOL CIN CCLK CI/O
PARAMETER Input Capacitance (except for CLK pins) Input Capacitance (CLK pins) DQ, DQS, DM Capacitance
MIN. 2 3 1.5
MAX. 4.5 5.5 6
UNIT pF pF pF
Note: These parameters are periodically sampled and not 100% tested.
Leakage and Output Buffer Characteristics
SYMBOL II(L) PARAMETER Input Leakage Current (0V < VIN < VDDQ, All other pins not under test = 0V) Output Leakage Current (Output disabled, 0V < VOUT < VDDQ) Output High Voltage (under AC test load condition) Output Low Voltage (under AC test load condition) Output Minimum Source DC Current Output Minimum Sink DC Current Full Strength -2 2 A MIN. MAX. UNITS NOTES
IO(L) VOH VOL IOH (DC) IOL (DC)
-5 VTT +0.76 -15.2 15.2
5 VTT -0.76 -
A V V mA mA 4, 6 4, 6
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W941232AD
DC Characteristics
SYM. PARAMETER
OPERATING CURRENT: One Bank Active-Read-Precharge; Burst=2; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address and control inputs changing once per clock cycle. PRECHARGE-POWER-DOWN STANDBY CURRENT: All Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM IDLE STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM ACTIVE POWER-DOWN STANDBY CURRENT: One Bank Active; Power down mode; CKE < VIL max; tCK = tCK min ACTIVE STANDBY CURRENT: CS > VIH min; CKE > VIH min; One Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 3; tCK = tCK min; IOUT = 0 mA OPERATING CURRENT: Burst = 2; Write; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 3; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle AUTO REFRESH CURRENT: tRC = tRFC min SELF REFRESH CURRENT: CKE < 0.2V
MAX.
-5
330 1
UNIT
NOTES
IDD1 IDD2P
mA mA
7, 9
IDD2N
58
mA
7
IDD3P
2
mA
IDD3N
210
mA
7
IDD4R
490
mA
7, 9
IDD4W IDD5 IDD6
410 350 1.5
mA mA mA
7 7
tCK = 10ns tRC
CK CK
tRCD
COMMAND ADDRESS DQS DQ Qa Qa Qb Qb Qb Qb Qc Qc Qc Qc Qd Qd (IDD7) Qd Qd Qe Qe ACT Bank 0 Row d READ AP Bank 3 Rowc Col c ACT Bank 1 Row e READ AP Bank 0 Rowd Col d ACT Bank 2 Row f READ AP Bank 1 Rowe Col e ACT Bank 3 Row q READ AP Bank 2 Col f ACT Bank 0 Row h
RANDOM READ CURRENT Timing
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Publication Release Date: January 24, 2003 Revision A1
W941232AD
8. AC CHARACTERISTICS AND OPERATING CONDITION (Notes: 10, 12)
SYMBOL
tRC tRFC tRAS tRCDR tRCDW tRAP tCCD tRP tRRD tWR tDAL tCK tAC tDQSCK tDQSQ tCH tCL tHP tQH tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tWPRES tWPRE tWPST tDQSS tIS tIH tIPW tHZ tLZ tT(SS) tWTR tXSRD tREF tMRD
PARAMETER
Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read Command Delay Time Active to Write Command Delay Time Active to Read with Auto Precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Auto Precharge Write Recovery + Precharge Time CLK Cycle Time Data Access Time from CLK, CLK DQS Output Access Time from CLK, CLK Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width CLK Half Period (minimum of actual tCH, tCL) DQ Output Data Hold Time from DQS DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Time DQ and DM Hold Time DQ and DM Input Pulse Width (for each input) DQS Input High Pulse Width DQS Input Low Pulse Width Clock to DQS Write Preamble Set-up Time DQS Write Preamble Time DQS Write Postamble Time Write Command to First DQS Latching Transition Input Setup Time Input Hold Time Control & Address Input Pulse Width (for each input) Data-out High-impedance Time from CLK, CLK Data-out Low-impedance Time from CLK, CLK SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to Read Command Refresh Time (4k) Mode Register Set Cycle Time CL = 3 CL = 4
-5
MIN. MAX.
UNITS
NOTES
65 75 40 20 10 20 1 20 10 10 30 5 -0.7 -0.7 0.45 0.45 Min. (tCL,tCH) tHP-0.45 0.9 0.4 0.45 0.45 2 0.4 0.4 0 0.25 0.4 0.8 1 1 2.5 -0.8 -0.8 0.5 1 200 64 10 0.8 0.8 1.5 tCK tCK mS nS nS 0.6 1.2 tCK 11 0.6 0.6 tCK nS 11 nS 1.1 0.6 10 0.7 0.7 0.45 0.55 0.55 tCK nS tCK 11 11 nS tCK 100000 nS
16
VDD/VDDQ =2.5V - 2.95V
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W941232AD
AC Test Conditions
SYMBOL VIH VIL VREF VTT VSWING Vr VID(AC) SLEW VOTR PARAMETER Input High Voltage (AC) Input Low Voltage (AC) Input Reference Voltage Termination Voltage Input Signal Peak to Peak Swing Differential Clock Input Reference Voltage Input Difference Voltage CLK and CLK inputs (AC) Input Signal Minimum Slew Rate Output Timing Measurement Reference Voltage VALUE VREF +0.31 VREF -0.31 0.5 x VDDQ 0.5 x VDDQ 1.0 Vx (AC) 1.5 1.0 0.5 x VDDQ UNIT V V V V V V V V/nS V NOTE
VDD/VDDQ =2.5V - 2.95V
VDDQ VIH min (AC) V SWING (MAX) VREF VIL max (AC) VSS
T T
VTT
Measurement point
RT= 50 ohms
output
Z = 50 ohms 30pF
Output
SLEW = (VIH min (AC) - VILmax (AC)) / T
A.C. TEST LOAD (A)
Notes: (1) (2) (3) Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. All voltages are referenced to VSS, VSSQ. Peak to peak AC noise on VREF may not exceed 2% VREF(DC).
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Publication Release Date: January 24, 2003 Revision A1
W941232AD
(4) (5) (6) (7) (8) (9) VOH = 1.95V, VOL = 0.35V VOH = 1.9V, VOL = 0.4V The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V. The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK and tRC. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. These parameters depend on the output loading. Specified values are obtained with the output open.
(10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed slope. (11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tDQSS = 0.75 x tCK, tCK = 5 nS, 0.75 x 5 nS = 3.75 nS is rounded up to 3.7 nS.) (12) VX is the differential clock cross point voltage where input timing measurement is referenced. (13) VID is magnitude of the difference between CLK input level and CLK input level.
(14) VISO means {VICK(CLK)+VICK( CLK )}/2. (15) Refer to the figure below.
CLK VX CLK VICK VSS VID(AC) VICK VX VX VICK VX VICK VX
VID(AC)
0 V Differential
VISO VISO(min) VSS VISO(max)
(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.
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W941232AD
Operation Mode
The following table shows the operation commands.
Simplified Truth Table
SYM. COMMAND DEVICE STATE CKEn-1 CKEn DM BA0, BA1 A8 A11-A9, A7-A0
CS
RAS
CAS
WE
ACT PRE PREA WRIT WRITA READ READA MRS EMRS NOP BST DSL AREF SELF SELEX
Bank Active Bank Precharge Precharge All Write Write with Auto Precharge Read Read with Auto Precharge Mode Register Set Extended Mode Regiser Set No Operation Burst Read Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Power Down Mode Entry Power Down Mode Exit Data Write Enable Data Write Disable
Idle
(3) (3)
H H H
X X X X X X X X X X X X H L H
X X X X X X X X X X X X X X X
V V X V V V V L, L H, L X X X X X X
V L H L H L H C V X X X X X X
V X X V V V V C V X X X X X X
L L L L L L L L L L L H L L H L H L H L X X
L L L H H H H L L H H X L L X H X H X H X X
H H H L L L L L L H H X L L X H X H X H X X
H L L L L H H L L H L X H H X X X X X X X X
Any
Any Active Active
(3)
H H H H H H H H H H H L
(3)
Active Active Idle Idle Any
(3)
(3)
Active Any Idle Idle Idle (Self Refresh) Idle/Active
(4)
PD
H
L
X
X
X
X
PDEX WDE WDD Notes: 1. 2. 3. 4.
Any (Power Down) Active Active
L H H
H X X
X L H
X X X
X X X
X X X
V = Valid
X = Don't Care
L = Low level
H = High level
CKEn signal is input level when commands are issued. CKEn-1 signal is input level one clock cycle before the commands are issued. These are state designated by the BA0, BA1 signals. Power Down Mode can not entry in the burst cycle.
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Publication Release Date: January 24, 2003 Revision A1
W941232AD
Function Truth Table (Note 1)
CURRENT STATE
CS RAS H L L X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L
CAS X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L
WE
ADDRESS
COMMAND
ACTION
NOTES
X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L
X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code
DSL NOP/BST READ/READ A WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP/BST READ/READ A WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READ A WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READ A WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS
Nop Nop ILLEGAL ILLEGAL Row activating Nop Refresh or Self refresh Mode register accessing Nop Nop Begin read: Determine AP Begin write: Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop Term burst, new read: Determine AP ILLEGAL ILLEGAL Term burst, precharging ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL Term burst, start Write: Determine AP ILLEGAL Term burst. precharging ILLEGAL ILLEGAL 6, 7 6 3 8 3 6 4 4 3 5 2 2 3 3
Idle
L L L L L H L L
Row active
L L L L L H L L L
Read
L L L L L H L L L
Write
L L L L L
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W941232AD
Function Truth Table (Continued)
CURRENT STATE CS RAS CAS WE ADDRESS COMMAND ACTION NOTES
H L L L Read with Auto Prechange L L L L L H L L L Write with Auto Precharge L L L L L H L L L Precharging L L L L L H L L L Row Activating L L L L L
X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L
X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L
X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L
X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code
DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS
Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop-> Idle after tRP Nop-> Idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop->Idle after tRP ILLEGAL ILLEGAL Nop-> Row active after tRCD Nop-> Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL 3 3 3 3 3 3 3 3 3 3 3
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Publication Release Date: January 24, 2003 Revision A1
W941232AD
Function Truth Table (Continued)
CURRENT STATE CS RAS CAS WE ADDRESS COMMAND ACTION NOTES
H L L Write Recovering L L L L L L H L Write Recovering with Auto Precharge L L L L L L L H L Refreshing L L L L H L Mode Register Accessing L L L
X H H H H L L L L X H H H H L L L L X H H H L L X H H H L
X H H L L H H L L X H H L L H H L L X H H L H L X H H L X
X H L H L H L H L X H L H L H L H L X H L H X X X H L X X
X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X X X X X X X X X
DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/WRIT ACT/PRE/PREA AREF/SELF/MRS/EMRS DSL NOP BST READ/WRIT ACT/PRE/PREA/AREF/ SELF/MRS/EMRS
Nop->Row active after tWR Nop->Row active after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop->Enter precharge after tWR Nop->Enter precharge after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop->Idle after tRC Nop->Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop->Row after tMRD Nop->Row after tMRD ILLEGAL ILLEGAL ILLEGAL 3 3 3 3 3 3 3 3
Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle. 2. Illegal if any bank is not idle. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. Illegal if tRCD is not satisfied. 5. Illegal if tRAS is not satisfied.
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W941232AD
6. 7. 8. Must satisfy burst interrupt condition. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. Must mask preceding data which don't satisfy tWR
Remark: H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data
Function Truth Table for CKE
CURRENT STATE CKE CS RAS CAS WE
n-1 H L
n X H H H H L X H L H L L L L L X H L L L L L X H X H L L L X X X X X H L L L L X X H L L L L X X X X H H L X X X X X X H L H L X X X H L H L X X X X H L X X X X X X X H L L X X X X H L L X X X X X X X X X X X X X X X H X X X X X X H X X X X
ADDRESS
ACTION
NOTES
X X X X X X X X X X X X X X X X X X X X X X X X
INVALID Exit Self Refresh->Idle after tXSNR Exit Self Refresh->Idle after tXSNR ILLEGAL ILLEGAL Maintain Self Refresh INVALID Exit Power down->Idle after tIS Maintain power down mode Refer to Function Truth Table Enter Power down Enter Power down Self Refresh ILLEGAL ILLEGAL Power down Refer to Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power down Refer to Function Truth Table 2 2 2 2 2 1
Self refresh
L L L L H
Power Down
L L H H H
All banks idle
H H H L H H H
Row Active
H H H L
Any state other than listed above Notes: 1. 2.
H
Self refresh can enter only from the all banks idle state. Power down can enter only from bank idle or row active state. H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data
Remark:
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Publication Release Date: January 24, 2003 Revision A1
W941232AD
9. FUNCTIONAL DESCRIPTION
1. Power Up Sequence
(1) Apply power and attempt to CKE at a low state ( 0.2V), all other inputs may be undefined 1) Apply VDD before or at the same time as VDDQ. 2) Apply VDDQ before or at the same time as VTT and VREF. (2) (3) (4) (5) (6) (7) (8) Start Clock and maintain stable condition for 200s(min). After stable power and clock, apply NOP and take CKE high. Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type. Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8. (an additional 200 cycles(min) of clock are required for DLL Lock) Issue precharge command for all banks of the device. Issue two or more Auto Refresh commands. Issue MRS-Initialize device operation. (If device operation mode is set at sequence 5, sequence 8 can be skipped.)
2. Command Function
2-1 Bank Activate command ( RAS = "L", CAS = "H", WE = "H", BA0, BA1 = Bank, A0 to A11 = Row Address) The Bank Activate command activates the bank designated by the BA (Bank address) signal. Row addresses are latched on A0 to A11 when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this command is issued, Read or Write operation can be executed. 2-2 Bank Precharge command ( RAS = "L", CAS = "H", WE = "L", BA0, BA1 = Bank, A8 = "L", A0 to A9, A11, A11 = Don't care) The Bank Precharge command percharges the bank designated by BA. The precharged bank is switched from the active state to the idle state. 2-3 Precharge All command ( RAS = "L", CAS = "H", WE ="L", BA0, BA1 = Don't care, A8 = "H", A0 to A9, A11, A11 = Don't care) The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state. 2-4 Write command ( RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A8 = "L", A0 to A9, A11 = Column Address) The write command performs a Write operation to the bank designated by BA. The write data are latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write operation. 2-5 Write with Auto Precharge command ( RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A8 = "H", A0 to A9, A11 = Column Address) - 16 -
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The Write with Auto Precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands. 2-6 Read command ( RAS = "H", CAS = "L", WE = "H", BA0, BA1 = Bank, A8 = "L", A0 to A9, A11 = Column Address) The Read command performs a Read operation to the bank designated by BA. The read data are synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Read operation. 2-7 Read with Auto Precharge command ( RAS = "H", CAS = "L", WE = "H", BA0, BA1 = Bank, A8 = "H", A0 to A9, A11 = Column Address) The Read with Auto precharge command automatically performs the Precharge operation after the Read operation. 1) READA tRAS (min) - (BL/2) x tCK Internal precharge operation begins after BL/2 cycle from Read with Auto Precharge command. 2) tRCD(min) READA < tRAS(min) - (BL/2) x tCK Data can be read with shortest latency, but the internal Precharge operation does not begin until after tRAS (min) has completed. This command must not be interrupted by any other command. 2-8 Mode Register Set command ( RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "L", A0 to A11 = Register Data) The Mode Register Set command programs the values of CAS latency, Addressing Mode, Burst Length and DLL reset in the Mode Register. The default values in the Mode Register after powerup are undefined, therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. Refer to the table for specific codes. 2-9 Extended Mode Register Set command ( RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L", A0 to A11 = Register data) The Extended Mode Register Set command can be implemented as needed for function extensions to the standard (SDR-SDRAM). Currently the only available mode in EMRS is DLL enable/disable, decoded by A0. The default value of the extended mode register is not defined; therefore this command must be issued during the power-up sequence for enabling DLL. Refer to the table for specific codes.
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2-10 No-Operation command ( RAS = "H", CAS = "H", WE = "H") The No-Operation command simply performs no operation (same command as Device Deselect). 2-11 Burst Read stop command ( RAS = "H", CAS = "H", WE = "L") The Burst stop command is used to stop the burst operation. This command is only valid during a Burst Read operation. 2-12 Device Deselect command ( CS = "H") The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command. 2-13 Auto Refresh command ( RAS = "L", CAS = "L", WE = "H", CKE = "L", BA0, BA1, A0 to A11 = Don't care) The Auto Refresh command is used to refresh the row address provided by the internal refresh counter. The Refresh operation must be performed 4096 times within 64ms. The next command can be issued after tREF from the end of the Auto Refresh command. When the Auto Refresh command is used, all banks must be in the idle state. 2-14 Self Refresh Entry command ( RAS = "L", CAS = "L", WE = "H", CKE = "L", BA0, BA1, A0 to A11 = don't care) The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self Refresh mode, all input and output buffer (except the CKE buffer) are disabled and the Refresh operation is automatically performed. Self Refresh mode is exited by taking CKE "high" (the Self Refresh Exit command). During self refresh, DLLl is disable. 2-15 Self Refresh Exit command (CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H") This command is used to exit from Self Refresh mode. Any subsequent commands can be issued after tXSNR (tXSRD for Read Command) from the end of this command. 2-16 Data Write Enable/ Disable command (DM = "L/H" or LDM, UDM = "L/H") During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to DQ15.
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3. Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available after CAS latency from the issuing of the Read command. The CAS latency must be set in the Mode Register at power-up. When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst operation is terminated. When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation.
4. Write Operation
Issuing the Write command after tRCD from the bank activate command. The input data is latched sequentially, synchronizing with both edges(rising &falling) of DQS after the Write command (Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up. When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated. When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto Precharge command cannot be interrupted by any other command for the entire burst data duration. Refer to the diagrams for Write operation.
5. Precharge
There are two Commands, which perform the precharge operation (Bank Precharge and Precharge All). When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged within tRAS(max) from the bank activate command. The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharge bank is then switched to the idle state.
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6. Burst Termination
When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of ( CAS latency) from the Precharge command. When the Burst Write cycle is interrupted by the Precharge command . the input circuit is reset at the same clock cycle at which the precharge command is issued. In this case, the DM signal must be asserted "high: during tWR to prevent writing the invalided data to the cell array. When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read operation is terminated. The Burst read Stop command is not supported during a write burst operation. Refer to the diagrams for Burst termination.
7. Refresh Operation
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed 4096 times(rows)within 64ms. The period between the Auto Refresh command and the next command is specified by tRFC. Self Refresh mode enter issuing the Self Refresh command (CKE asserted "low"). while all banks are in the idle state. The device is in Self Refresh mode for as long as cke held "low". In the case of 4096 burst Auto Refresh commands, 4096 burst Auto Refresh commands must be performed within 15.6us before entering and after exiting the Self Refresh mode. In the case of distributed Auto Refresh commands, distributed auto refresh commands must be issued every 15.6us and the last distributed Auto Refresh commands must be performed within 15.6us before entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within 15.6us. In Self Refresh mode, all input/output buffers are disable, resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh operation.
8. Power Down Mode
Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode and Precharge Standby Power Down Mode. When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting in low power dissipation (except CKE buffer). Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking cke :high" can exit this mode. When CKE goes high, a No operation command must be input at next CLK rising edge. Refer to the diagrams for Power Down Mode.
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9. Mode Register Operation
The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A11 and BA0, BA1 address inputs. The Mode Register designates the operation mode for the read or write cycle. The register is divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in clock cycle (4) DLL reset field to reset the dll (5) Regular/Extended Mode Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL enable/Disable mode) The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the Mode Register Set command must be issued before power operation. (1) Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2, 4, and 8 words. A2 0 0 0 0 1 A1 0 0 1 1 x A0 0 1 0 1 x Burst Length Reserved 2 words 4 words 8 words Reserved
(2) Addressing Mode Select (A3) The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both addressing Mode support burst length 2, 4, and 8 words. A3 0 0 Addressing mode Sequential Interleave
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Publication Release Date: January 24, 2003 Revision A1
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* Address sequence of Sequential mode A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as the following. Addressing Sequence of Sequential Mode DATA Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 * ACCESS ADDRESS n n+1 n+2 n+3 n+4 n+5 n+6 n+7 8 words(address bits A2, A1 and A0) Not carried from A2 to A3 BURST LENGTH 2 words (address bits is A0) not carried from A0 to A1 4 words (address bit A0, A1) Not carried from A1 to A2
Addressing sequence of Interleave mode A Column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. Address Sequence for Interleave Mode DATA Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 ACCESS ADDRESS A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 8 words 4 words BURST LENGTH 2 words
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(3) CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depends on the frequency of CLK. A6 0 0 0 0 1 1 1 1 (4) DLL Reset bit (A8) This bit is used to reset DLL. When the A8 bit is "1", DLL is reset. (5) Mode Register /Extended Mode register change bits (BA0, BA1) These bits are used to select MRS/EMRS. BA1 BA0 0 0 0 1 1 x (6) Extended Mode Register field 1) DLL Switch field (A0) This bit is used to select DLL enable or disable A0 0 1 DLL Enable Disable A11 - A0 Regular MRS cycle Extended MRS cycle Reserved A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved Reserved 3 4 Reserved Reserved Reserved
2) Output Driver Size Control field (A1, A6) This bit is used to select Output Driver Size, A6 0 0 1 1 A1 0 1 0 1 Output driver Full strength 60% strength Reserved 30% strength
(7) Reserved field * Test mode entry bit (A7) This bit is used to enter Test mode and must be set to "0" for normal operation. * Reserved bits (A9, A8, A11) These bits are reserved for future operations. They must be set to "0" for normal operation. Publication Release Date: January 24, 2003 Revision A1
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MODE REGISTER DEFINITION BA0 BA1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 0*
12 0*
10
9
8
7
6
5
4
3 BT
2
1
0
Extended Mode Register
Operating Mode
CAS Latency
Burst Latency
* BA0 and BA1 must be 0, 0 to select the Mode Register (vs. the Extended Mode Register).
A2 A1 A0 000 001 010 011 100 101 110 111 A3 0 1
Burst Latency A3 = 0 A3 = 1 Reserved Reserved 2 2 4 4 8 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Burst Type Sequential Interleaved
A6 0 0 0 0 1 1 1 1 An-A9 0 0 0 -
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved Reserved 3 4 Reserved Reserved Reserved
A8 A7 A6-A0 0 0 Valid 1 0 Valid 0 1 VS --
Operating Mode Normal Operation Normal Operation/Reset DLL Vendor Specific Test Mode All other states reserved
VS = Vendor Specific
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EXTENDED MODE REGISTER DEFINITION BA0 BA1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
12
11 10
9
8
7
6
5
4
3
2
1
0
Extended Mode Register
1* 0* Operating Mode DS1 Operating Mode DS0 DLL * BA0 and BA1 must be 1, 0 to select the Extended Mode Register (vs. the base Mode Register).
A0 0 1
DLL Enable Disable
A6 A1 0 0 1 1 0 1 0 1
Drive Strength Full Weak (60%) 30%
A10-A7,A5-A2 0 -
A1,A2,A6 Valid -
Operating Mode Normal Operation All other states reserved
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Publication Release Date: January 24, 2003 Revision A1
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Simplified State Diagram
SELF REFRESH
SREF SREFX
IDLE
MRS/EMRS
MODE REGISTER SET
AREF
AUTO REFRESH
PD PDEX ACT
ACTIVE POWERDOWN POWER DOWN
PDEX PD
ROW ACTIVE
BST Read Read
Write
Write
Write
Read
Read
Write A Write A
Read A Read A
PRE
Write A
PRE
PRE
Read A
POWER APPLIED
POWER ON
PRE
PRE CHARGE
Automatic Sequence Command Sequence
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10. TIMING WAVEFORMS
Command Input Timing
tCK tCK CLK CLK tIS CS tIH tCH tCL
tIS RAS
tIH
tIS CAS
tIH
tIS WE
tIH
tIS A0~A11 BA0, 1
tIH
Refer to the Command Truth Table
Timing of the CLK signals
CLK CLK tCK CLK CLK VX VX VX VIH VIL tCH tCL VIH VIH(AC) VIL(AC) VIL
tT
tT
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Publication Release Date: January 24, 2003 Revision A1
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11. PACKAGE DIAMENSION
H D D
E
H
E
e
b
c
A2 A See Detail F A1 y L L1
Seating Plane
Controlling dimension : Millimeters
Symbol
Dimension in inch
Dimension in mm
Min Nom Max
0.002 0.004 0.053 0.055 0.009 0.013 0.004 0.006 0.547 0.551 0.783 0.787 0.020 0.026 0.626 0.862 0.018 0.630 0.866 0.024 0.039 0.003 0 7 0.006 0.057 0.015 0.008 0.555 0.791 0.032 0.634 0.870 0.030
Min Nom Max
0.05 1.35 0.22 0.10 13.90 19.90 0.10 1.40 0.32 0.15 0.15 1.45 0.38 0.20
A A1 A2 b c D E e HD HE L L1 y
14.00 14.10 20.00 20.10 0.802 16.10 22.10 0.75 16.00 22.00 0.60 1.00 0.08
0.498 0.65 15.90 21.90 0.45
0
7
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12. VERSION HISTORY
VERSION A1 DATE Jan. 24, 2003 PAGE Datasheet DESCRIPTION
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: January 24, 2003 Revision A1

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